Semiconductor memory integrated circuits have traditionally utilized an internal architecture defined in an array having rows and columns, with the row-column address intersections defining individual data storage locations or memory cells. Typically, these intersections are addressed through an internal address bus, and the data to be stored or read from the locations is transferred to an internal input/output bus. Groups of data storage locations are normally coupled together along word lines. Semiconductor configurations utilizing this basic architecture include dynamic random access memory (DRAM), static random access memory (SRAM), electrically programmable read only memory (EPROM), erasable EPROM (EEPROM), as well as “flash” memory.
One of the more important measures of performance for such memory devices is the total usable data bandwidth. The main type of timing delay affecting the data bandwidth is referred to as access time. Access time is defined as the delay between the arrival of new address information at the address bus and the availability of the accessed data on the input/output bus.
In order to either read data from or write data to a DRAM memory array, a number of sequential operations are performed. Initially, bit line pairs are equalized and pre-charged. Next, a selected word line is asserted in order to read out the charge state of an addressed memory cell onto the bit lines. Bit line sense amplifiers are then activated for amplifying a voltage difference across the bit line pairs to full logic levels. Column access transistors, which are typically n-channel pass transistors, are then enabled to either couple the bit line state to DRAM read data amplifiers and outputs, or to over-write the bit line state with new values from DRAM write data inputs.
In nearly all DRAM architectures, the two dimensional nature of the memory array addressing is directly accessible to the external memory controller. In asynchronous DRAM architectures, separate control signals are used for controlling the row (or x-address) and column (or y-address) access operations. In synchronous DRAM architectures, it is also possible to use separate row and column control signals as described above. Furthermore, for synchronous DRAM architectures it is possible to employ a single command path for both row and column control signals.
In these cases, bit line sense amplifier activation is usually performed as the last stage of a self-timed sequence of DRAM operations initiated by a row activation command. Column access transistors are controlled by the y-address decoding logic and are enabled by the control signals associated with individual read and write commands.
However, for both asynchronous and synchronous DRAM architectures, the ability to minimize the timing margin between bit line sensing and the enabling of the column access transistors is limited by the timing variability between the separate control paths for row access and column access operations. Even in synchronous designs, the x-address and y-address decoding logic paths are quite distinct. The timing variability between the completion of bit line sensing and the commencement of column access transistor activation comprises the sum of the variability between the x and y address decoding paths, the variability of the self-timed chain that activates the bit line sense amplifiers, and the time of flight differences in control signals. That is, the control signals arrive at a given memory array from row and column control logic located in separate regions of the memory device and therefore may have different activation timing.
In order to reduce DRAM access times and increase the rate at which read and write operations can be performed it is important to attempt to reduce the time needed for each of the previously mentioned sequential operations necessary for the functioning of a DRAM. Furthermore, equally important is the need to initiate each successive DRAM access function as soon as possible after the previous operation.
Specifically, the delay between bit line restoration and the enabling of the column activation device is critical for both correct DRAM operation and achieving low access latency. If the column access transistor is enabled too soon, the memory cell read out on to the bit lines may be corrupted. The corruption can occur directly from noise on the bit lines coupled through the column access transistors or indirectly through capacitive coupling between a bit line driven through the column access transistor and an adjacent unselected bit line. Since the data is read destructively, if it is corrupted, it cannot be retrieved. On the other hand, if the column access transistor is enabled too late, unnecessary delay is added to memory access latency. Furthermore, the equalization and pre-charge of the bit lines in preparation for a subsequent access operation may effectively be unable to proceed until the column access transistors are turned off.
Therefore, there is a need for a memory device that can initiate successive DRAM access functions with little or no unnecessary delay without corrupting memory cell data. Accordingly, it is an object of the present invention to obviate or mitigate at least some of the above mentioned disadvantages.